In various types of electronic devices, synchronous serial data signals may be provided without a separate clock signal. In such implementations, a device receiving a serial data signal may be required to perform synchronization using only the serial data signal without the aid of a separate dedicated clock signal.
For example, in one approach (e.g., in conventional analog serializer/deserializer (SERDES) applications), a receiving device may adjust the speed of its local clock to properly synchronize with a serial data signal. However, such an approach may be impractical to implement in certain types of devices such as programmable logic devices (PLDs) including field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs).
For PLDs, an alternate approach may be used in which data provided by the serial data signal is synchronized with an existing stable local clock of a PLD. For example, a serial data signal received by one input (e.g., a low-voltage differential signaling input) of a PLD may be oversampled (e.g., four times oversampled) by the FPGA, and the data encoded in the serial data signal may be extracted from the samples. Unfortunately, this approach can be problematic when high speed serial data signals are received. For example, at serial data speeds in excess of approximately 200 Mbps, system skew and jitter may exceed approximately ¼ of a clock cycle, thus making it extremely difficult to extract the data from the serial data signal.
Accordingly, there is a need for an improved approach to the synchronization of serial data signals. In particular, there is a need for such an approach that addresses the concerns associated with the synchronization of such serial data signals with PLDs.